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this is information on a product in full production. september 2012 doc id 17526 rev 2 1/26 26 ST7570 s-fsk power line networking system-on-chip datasheet ? production data features fully integrated narrow-band power line networking system-on-chip high performing phy processor with embedded turn-key firmware for spread frequency shift keying (s-fsk) modulation: ? programmable bit rate up to 2.4 kbps (@ 50 hz) ? 1 hz step programmable carriers up to 148.5 khz ? signal to noise ratio estimation ? received signal strength indication protocol engine embedding: ? iec61334-5-1 phy and mac layers ? alarm management ? repeater call procedure ? intelligent search initiator process on chip peripherals: ? host controller uart interface fully integrated analog front end: ? adc and dac ? pga with automatic gain control for high receiving sensitivity ? high linearity modulated signal generation fully integrated single-ended power amplifier for line driving ? up to 1 a rms, 14 v p-p output ? configurable active filtering topology ? very high linearity ? embedded temperature sensor ? current control feature 8 to 18 v power amplifier supply 3.3 v or 5 v digital i/o supply integrated 5 v and 1.8 v linear regulators for afe and digital core supply mains zero crossing synchronization suitable for en50065 and fcc part 15 compliant applications vfqfpn48 package with exposed pad -40 c to +85 c temperature range applications smart metering applications street lighting control command and control networking description the ST7570 is a powerful power line networking system-on-chip. it combines a high-performance phy processor core and a protocol controller core with a fully integrated analog front end (afe) and line driver. the ST7570 features allow the most cost- effective, single-chip power line communication solution based on iec61334-5-1 s-fsk standard. table 1. device summary order codes package packaging ST7570 vfqfpn48 tube ST7570tr tape and reel 6&1&0.xx, pitch www.st.com
contents ST7570 2/26 doc id 17526 rev 2 contents 1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 analog front end (afe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 reception path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 transmission path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 current and voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 thermal shutdown and temperature control . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 zero-crossing pll and delay compensation . . . . . . . . . . . . . . . . . . . . . . 16 6 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.1 s-fsk principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.2 bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.3 frame structure at physical level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.4 frame timing and time-slot synchronization . . . . . . . . . . . . . . . . . . . . . . . 22 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ST7570 device overview doc id 17526 rev 2 3/26 1 device overview realized using a multi-power technology with state-of-the-art vlsi cmos lithography, the ST7570 is based on dual digital core architecture (a phy processor engine and a protocol controller core) to guarantee outstanding communication performance with a high level of flexibility and programmability. the on-chip analog front end, featuring analog to digital and digital to analog conversion and automatic receiver gain control, plus the integrated power amplifier delivering up to 1arms output current, makes the ST7570 the first complete system-on-chip for power line communication. line coupling network design is also simplified, leading to a very low cost bom. safe and performing operations are guaranteed while keeping power consumption and distortion levels very low, thus making ST7570 an ideal platform for the most stringent application requirements and regulatory standards compliance. figure 1. block diagram 7!4 #($/' 4)-%23 0ower-anagement !$# 0'! $!# '!). #4 2, $$3 :ero#rossing$etection ,ine$river 4hermal -anagement #loc k-anagement 0rotocol #ontroller 48!&% 0(90rocessor "0& "0& /utput#urrent #ontrol 5!24 !$# 28!&% 48? / 5 4 28? ) . 0! ? / 5 4 0! ?). 6## 6 #, 6$$ 6 :#?). ?! :#?). ?$ 6$$?0,, 6 8). 8/54 6##! 6 4?2%1 28$ 48$ "2 "2 02%3,/4:#43")4 6 $$)/ 6 /. #()0 -emories /. #()0 -emories 0! 0! ? ) . !-v
pin connection ST7570 4/26 doc id 17526 rev 2 2 pin connection figure 2. pin out top view !-v ? ? e ? ? ? ? ? ?? ?e ?? ?? ? ? ?? ?? ? ? ?? e? e e e? ee e? e? e e ?? ?? ? ? e ? ? ? ? ? ?? ?? ?e dy s/k dz^d e dd^ d < dk d/ z^de s y/e wz^>kdlld^l/d s^^ s/k 'e e z^zs e e s/k szz'zs? wzkhd s^^ z^zs? z^zse s 'e z^zs? z^zs? z^zs z^zs z z dzzy z/ez ykhd 'e s^^ szw>> s zyz/e dyzkhd wz/e= wz/er > s 'e zy z/e z
ST7570 pin connection doc id 17526 rev 2 5/26 2.1 pin description table 2. pin description pin name type reset state pull-up description 1 txd digital output high z disabled uart data out external pull-up to vddio required 2 rxd digital input high z disabled uart data in 3 vddio power - - 3.3 v ? 5 v i/o external supply 4 trstn digital input input enabled system jtag interface reset (active low) 5 tms digital input input enabled system jtag interface mode select 6 gnd power - - digital ground 7 tck digital input high z disabled system jtag interface clock. external pull-up to vddio required 8 tdo digital output high z disabled system jtag interface data out 9 tdi digital input input enabled system jtag interface data in 10 resetn digital input input disabled system reset (active low) 11 vdd power - - 1.8 v digital supply. internally connected to vdd_reg_1v8 externally accessible for filtering purposes only 12 xin analog - - crystal oscillator input / external clock input 13 xout analog - - crystal oscillator output (if external clock supplied on xin, xout must be left floating) 14 gnd power - - digital ground 15 vssa power - - analog ground 16 vdd_pll power - - 1.8 v pll supply voltage. connect externally to vdd 17 vcca power - - 5 v analog supply / internal regulator output externally accessible for filtering purposes only 18 zc_in_a analog input - - analog zero-crossing input 19 rx_in analog input - - reception analog input 20 tx_out analog output - - transmission analog output 21 pa_in+ analog input - - power amplifier non-inverting input 22 pa_in- analog input - - power amplifier inverting input 23 cl analog input - - current limit sense input 24 vcc power - - power supply 25 vss power - - power ground
pin connection ST7570 6/26 doc id 17526 rev 2 26 pa_out analog output - - power amplifier output 27 vdd_reg_1v8 power - - 1.8 v digital supply / internal regulator output externally accessible for filtering purposes only 28 vddio power - - 3.3 v ? 5 v i/o external supply 29 nc - - - not used, leave floating 30 nc - - - not used, leave floating 31 reserved6 - - - pull up to vddio 32 nc - - - not used, leave floating 33 gnd power - - digital ground 34 vddio power - - 3.3 v ? 5 v i/o supply 35 vssa power - - analog ground 36 preslot /zc/ts/bit digital output high z disabled configurable digital output: - slot synchronization (preslot), - zero crossing (zc), - timeslot (ts), - bit synchronization (bit), - transmission in progress (txp), - reception in progress (rxp), - transmission or reception in progress (txrxp). if not used, this pin can be left floating. 37 zc_in_d digital input high z disabled digital zero-crossing input. pull up to vddio if not used 38 t_req digital input high z disabled uart communication control line 39 br1 digital input high z disabled uart baud rate selection (sampled after each reset event) see ta b l e 3 40 br0 digital input high z disabled 41 reserved0 - - - connect to gnd 42 reserved1 - - - pull up to vddio 43 reserved2 - - - pull up to vddio 44 reserved3 - - - pull up to vddio 45 gnd power - - digital ground 46 vdd power - - 1.8 v digital supply. internally connected to vdd_reg_1v8 externally accessible for filtering purposes only 47 reserved4 - - - connect to vddio 48 reserved5 - - - pull up to vddio table 2. pin description (continued) pin name type reset state pull-up description
ST7570 pin connection doc id 17526 rev 2 7/26 table 3. uart baud rate selection br1 br0 baud rate 0 0 9600 0 1 19200 1 0 38400 1 1 57600
maximum ratings ST7570 8/26 doc id 17526 rev 2 3 maximum ratings 3.1 absolute maximum ratings 3.2 thermal data figure 3. absolute maximum ratings symbol parameter value unit min max vcc power supply voltage -0.3 20 v vssa-gnd voltage between vssa and gnd -0.3 0.3 v vddio i/o supply voltage -0.3 5.5 v vi digital input voltage gnd-0.3 vddio+0.3 v vo digital output voltage gnd-0.3 vddio+0.3 v v(pa_in) pa inputs voltage range vss-0.3 vcc+0.3 v v(pa_out) pa_out voltage range vss-0.3 vcc+0.3 v v(rx_in) rx_in voltage range -(vcca+0.3) vcc+0.3 v v(zc_in_a) zc_in_a voltage range -(vcca+0.3) vcca+0.3 v v(tx_out, cl) tx_out, cl voltage range vssa-0.3 vcca+0.3 v v(xin) xin voltage range gnd-0.3 vddio+0.3 v i(pa_out) power amplifier output non-repetitive peak current 5 a peak i(pa_out) power amplifier output non-repetitive rms current 1.4 a rms t amb operating ambient temperature -40 85 c t stg storage temperature -50 150 c v(esd) maximum withstanding voltage range test condition: cdf-aec-q100-002 ?human body model? acceptance criteria: ?normal performance? -2 +2 kv table 4. thermal characteristics symbol parameter value unit r thja1 maximum thermal resistance junction-ambient steady state (1) 1. mounted on a 2-side + vias pcb with a ground dissipating area on the bottom side. 50 c/w r thja2 maximum thermal resistance junction-ambient steady state (2) 2. same conditions as in note 1, with maximum transmission duration limited to 100 s. 42 c/w
ST7570 electrical characteristics doc id 17526 rev 2 9/26 4 electrical characteristics t a = -40 to +85c, t j < 125c, v cc = 18 v unless otherwise specified. table 5. electrical characteristics symbol parameter note min. typ. max. unit power supply vcc power supply voltage 8 13 18 v i(vcc) rx power supply current - rx mode vcca externally supplied 0.35 0.5 ma i(vcc) tx power supply current - tx mode, no load vcca externally supplied 22 30 ma vcc uvlo_tl vcc under voltage lock out low threshold 6.1 6.5 6.95 v vcc uvlo_th vcc under voltage lock out high threshold 6.8 7.2 7.5 v vcc uvlo_hyst vcc under voltage lock out hysteresis 250 (1) 700 mv i(vcca) rx analog supply current - rx mode 5 6 ma i(vcca) tx analog supply current - tx mode v(tx_out) =5 v p-p, no load 8 10 ma i(vdd) digital core supply current 35 41 ma i(vdd) reset digital core supply current in reset state 8 ma vdd_pll pll supply voltage vdd v i(vdd_pll) pll supply current 0.4 0.45 ma vddio digital i/o supply voltage externally supplied -10% 3.3 or 5 +10% v vddio uvlo_tl vddio under voltage lock out low threshold 2.2 2.4 2.6 v vddio uvlo_th vddio under voltage lock out high threshold 2.45 2.65 2.85 v vddio uvlo_hyst vddio under voltage lock out hysteresis 180 240 mv analog front end power amplifier v(pa_out) bias power amplifier output bias voltage - rx mode vcc/2 v gbwp power amplifier gain-bandwidth product 100 mhz i(pa_out) max power amplifier maximum output current 1000 ma rms
electrical characteristics ST7570 10/26 doc id 17526 rev 2 v(pa_out) tol power amplifier output tolerance (2) vcc=18 v, v(pa_out) = 14 v p- p (typ), v(pa_out) bias = vcc/2, r load =50 , t = 25c see figure 3 -3% +3% v(pa_out) hd2 power amplifier output 2nd harmonic distortion -70 -63 dbc v(pa_out) hd3 power amplifier output 3rd harmonic distortion -66 -63 dbc v(pa_out) thd power amplifier output total harmonic distortion 0.1 0.15 % c(pa_in) power amplifier input capacitance pa_in+ vs. vss (3) 10 pf pa_in- vs. vss (3) 10 pf psrr power supply rejection ratio 50 hz 100 db 1 khz 93 db 100 khz 70 db cl_th current sense high threshold on cl pin 2.25 2.35 2.4 v cl_ratio ratio between pa_out and cl output current. 80 transmitter v(tx_out) bias transmitter output bias voltage - rx mode vcca/ 2 v v(tx_out) max transmitter output maximum voltage swing tx_gain = 31, no load 4.8 4.95 vcca v p-p tx_gain transmitter output digital gain range 0 31 tx_gain tol transmitter output digital gain tolerance -0.35 0.35 db r(tx_out) transmitter output resistance 1 k v(tx_out) hd2 transmitter output 2nd harmonic distortion v(tx_out) = 4.5 vpkpk (typ.), no load, t = 25c -72 -55 dbc v(tx_out) hd3 transmitter output 3rd harmonic distortion -70 -67 dbc v(tx_out) thd transmitter output total harmonic distortion 0.1 0.2 % receiver v(rx_in) max receiver input maximum voltage vcc = 18 v 16 v p-p v(rx_in) bias receiver input bias voltage vcca/ 2 v z(rx_in) receiver input impedance 10 k v(rx_in) min receiver input sensitivity bit rate = 1200 bps @ 50 hz, ber = 10-3, snr = 20 db 45 dbv rms table 5. electrical characteristics (continued) symbol parameter note min. typ. max. unit
ST7570 electrical characteristics doc id 17526 rev 2 11/26 pga_min pga minimum gain -18 db pga_max pga maximum gain 30 db oscillator v(xin) oscillator input voltage swing clock frequency supplied externally 1.8 vddio v p-p v(xin) th oscillator input voltage threshold 0.8 0.9 1 v f(xin) crystal oscillator frequency 8 mhz f(xin) tol external quartz crystal frequency tolerance -150 +150 ppm esr external quartz crystal esr value 100 c l external quartz crystal load capacitance 16 20 pf f clk _afe internal frequency of the analog front end 8 mhz f clk _prot_ctrl internal frequency of the protocol ctrl core 28 mhz f clk _phy_proces sor internal frequency of the phy processor core 56 mhz temperature sensor t_th 1 temperature threshold 1 63 70 77 c t_th 2 temperature threshold 2 90 100 110 c t_th 3 temperature threshold 3 112 125 138 c t_th 4 temperature threshold 4 153 170 187 c zero crossing comparator v(zc_in_a) max zero crossing analog input voltage range 10 v p-p v(zc_in_a) tl zero crossing analog input low threshold -40 -30 -20 mv v(zc_in_a) th zero crossing analog input high threshold 30 40 50 mv v(zc_in_a) hyst zero crossing analog input hysteresis 62 70 78 mv zc_in_d d.c. zero crossing digital input duty cycle 50 % digital section digital i/o table 5. electrical characteristics (continued) symbol parameter note min. typ. max. unit
electrical characteristics ST7570 12/26 doc id 17526 rev 2 figure 4. power amplifier test circuit r pull-up internal pull-up resistors vddio = 3.3 v 66 k vddio = 5 v 41 k vih high logic level input voltage 0.65*v ddio vddio +0.3 v vil low logic level input voltage -0.3 0.35*v ddio v voh high logic level output voltage ioh= -4 ma vddio -0.4 v vol low logic level output voltage iol= 4 ma 0.4 v uart interface baud rate -1.5% 57600 +1.5% bau d -1.5% 38400 +1.5% bau d -1.5% 19200 +1.5% bau d -1.5% 9600 +1.5% bau d reset and power on t resetn minimum valid reset pulse duration 1 s t startup start-up time at power on or after a reset event 60 ms 1. referred to t a = -40 c 2. this parameter does not include t he tolerance of external components 3. guaranteed by design table 5. electrical characteristics (continued) symbol parameter note min. typ. max. unit
ST7570 analog front end (afe) doc id 17526 rev 2 13/26 5 analog front end (afe) 5.1 reception path figure 4 shows the block diagram of the ST7570 input receiving path. the main blocks are a wide input range analog programmable gain amplifier (pga) and the analog to digital converter (adc). figure 5. reception path block diagram the pga is controlled by an embedded loop algorithm, adapting the pga gain to amplify or attenuate the input signal according to the input voltage range for the adc. the pga gain ranges from -18 db up to 30 db, with steps of 6 db (typ.), as described in ta b l e 5 . 5.2 transmission path figure 5 shows the transmission path block diagram. it is mainly based on a digital to analog converter (dac), capable to generate a linear signal up to its full scale output. a gain control block before the dac gives the possibility to scale down the output signal to match the desired transmission level. table 6. pga gain table pga code pga gain (typ) [db] rx_in max range [v p-p] 0-1816 1-128 2-64 302 461 5 12 0.500 6 18 0.250 7 24 0.125 8 30 0.0625 !-v 5;$)( %3) $'& 5;b,1 %3) %3) $'& $'& 3*$ 3*$
analog front end (afe) ST7570 14/26 doc id 17526 rev 2 figure 6. transmission path block diagram the amplitude of the transmitted signal can be set on a 32-step logarithmic scale through the tx_gain parameter, introducing an attenuation ranging from 0 db (typ.), corresponding to the tx_out full range, down to -31 db (typ.). the attenuation set by the tx_gain parameter can be calculated using the formula of equation 1: equation 1 output attenuation a [db] vs. tx gain 5.3 power amplifier the integrated power amplifier is characterized by very high linearity, required to be compliant with the different international regulations (cenelec, fcc etc.) limiting the spurious conducted emissions on the mains, and a current capability of 1 a rms that allows the amplifier driving even very low impedance points of the network. all the pins of the power amplifier are accessible, making it possible to build an active filter network to increase the linearity of the output signal. !-v 7;$)( '$& *dlq &rq wuro 7;b287 7;b*$,1 %3) %3) adb [] tx_gain 31 ? () tx_gain tol + =
ST7570 analog front end (afe) doc id 17526 rev 2 15/26 5.4 current and voltage control the power amplifier output current sensing is performed by mirroring a fraction of the output current and making it flow through a resistor r cl connected between the c l pin and vss. the following relationship can be established between v(cl) and i(pa_out): equation 2 v(cl) vs. i(pa_out) the voltage level v(cl) is compared with the internal threshold cl_th. when the v(cl) exceeds the cl_th level, the v(tx_out) voltage is decreased by one tx_gain step at a time until v(cl) goes below the cl_th threshold. the current sense circuit is depicted in figure 6 . figure 7. pa_out current sense circuit the r cl value to get the desired output current limit i(pa_out)lim can be calculated according to equation 3: equation 3 r cl calculation note that i(pa_out) lim is expressed as peak current, so the corresponding rms current value shall be calculated according to the transmitted signal waveform. the r cl value to get 1 a rms output current limit, calculated with typical values for cl_th and cl_ratio parameters, is indicated in ta b l e 7 . table 7. cl resistor typical values parameter description value unit r cl resistor value for i(pa_out) max = 1 a rms (1.41 a peak) 133 vcl () r cl i pa_out () ? cl_ratio ------------------------------------------------ - = !-v 3$ &/ 9&& &/ ,&/ ,3$b287&/b5$7,2 3$ ,3$b287 5 r cl cl_th i(pa_out) lim cl_ratio ? -------------------------------------------------------------------------- - =
analog front end (afe) ST7570 16/26 doc id 17526 rev 2 5.5 thermal shutdown and temperature control the ST7570 performs an automatic shutdown of the power amplifier circuitry when the internal temperature exceeds t_th 4 . after a thermal shutdown event, the temperature must get below t_th 3 before the ST7570 power amplifier comes back to operation. moreover, a digital thermometer is embedded to identify the internal temperature among four zones, as indicated in ta b l e 8 . table 8. temperature zones 5.6 zero-crossing pll and delay compensation in operating mode, ST7570 needs to be synchronized with an external signal period through zero crossing detection. the user can select among two input pins for the external zero-crossing reference: analog input (zc_in_a): it requires a bipolar analog input signal which is internally squared through a schmidt trigger comparator with symmetrical thresholds; digital input (zc_in_d): it requires a 50% duty-cycle square-wave digital signal (with two levels). the desired input can be selected by accessing a dedicated management information base (mib) object. the ST7570 embeds a phase-locked loop (pll) to generate the internal reference based on the external zero-crossing. in case of delay due to external zero crossing coupling circuits (i.e. based on optocouplers) or to improve interoperability, it is possible to introduce delay compensation through a dedicated mib object. figure 8. zero crossing detection temperature zone temperature value 1t < t_th 1 2t_th 1 < t < t_th 2 3t_th 2 < t < t_th 3 4t > t_th 3 !-v =&b,1b' =&b,1b' frqiljxudwlrq elw 0,%remhfw ,qwhuqdo 5hihuhqfh 3// 6fkplgw 7uljjhu =&b,1b$
ST7570 power management doc id 17526 rev 2 17/26 6 power management figure 9 shows the power supply structure for the ST7570 device. the ST7570 operates from two external supply voltages: vcc (8 to 18 v) for the power amplifier and the analog section; vddio (3.3 or 5 v) for interface lines and digital blocks. two internal linear regulators provide the remaining required voltages: 5 v analog front end supply: generated from the vcc voltage and connected to the vcca pin; 1.8 v digital core supply: generated from the vddio voltage and connected to vdd_reg_1v8 (direct regulator output) and vdd pins. the vdd_pll pin, supplying the internal clock pll, must be externally connected to vdd. all supply voltages must be properly filtered to their respective ground, using external capacitors close to each supply pin, in accordance to the supply scheme depicted in figure 9 . note that the internal regulators connected to vdd_reg_1v8 and to vcca are not designed to supply external circuitry; their outputs are externally accessible for filtering purpose only. figure 9. power supply internal scheme !-v 6##! 633 6$$)/ '.$ 6$$?2%'?6 !&% $)')4! ,#/2% 0! $)')4! ,).4%2&!#%3 6$$ 633! 6$$?0,, ).4%2.!,0,, ,$/ ,$/ 6## 63 3! '.$
clock management ST7570 18/26 doc id 17526 rev 2 7 clock management the main clock source is an 8 mhz crystal connected to the internal oscillator through xin and xout pins. both xin and xout pins have a 32 pf integrated capacitor, in order to drive a crystal having a load capacitance of 16 pf with no additional components. alternatively, an 8 mhz external clock can be directly supplied to xin pin, leaving xout floating. a pll internally connected to the output of the oscillator generates the f clk_phy , required by the phy processor block. f clk_phy is then scaled down by two to obtain f clk_pc , required by the protocol controller. 8 functional overview the ST7570 embeds complete physical (phy) and a medium access control (mac) protocol layers and services compliant with the open standard iec61334-5-1, mainly developed for smart metering applications, but suitable also for other command and control applications and remote load management in cenelec b and d bands. a local port (uart) is available for communication with an external host, exporting all the functions and services required to configure and control the device and its protocol stack. below a list of the protocol layers and functions embedded in the ST7570 ( figure 10 ): physical layer: implemented in the phy processor and exporting all the primitive functions listed in the international standard document iec61334-5-1, plus additional services for configuration, alarm management, signal and noise amplitude estimation, phase detection, statistical information; mac layer: implemented on the protocol controller and exporting all the primitive functions listed in the international standard document iec61334-5-1, repeater call and intelligent search initiator process together with additional services. management information base (mib): an information database with all the data required for proper configuration of the system (at both phy and mac layer); host interface: all the services of the phy, mac and mib are exported to an external host through the local uart port.
ST7570 functional overview doc id 17526 rev 2 19/26 figure 10. functional overview 8.1 references additional information regarding the phy and mac layers, the mib and the host interface, including a detailed description of all services, extended functionalities and commands can be found in the following documents: 1. ST7570 user manual, www.st.com/powerline 2. international standard cei-iec-61334-5-1 !-v 0(9,ayer (/34)nterface 0(9 0rocessor 0rotocol#ontroller -!#,ayer -)" 34 ,ocal0ort 5!24 48$ 28$ 4?2%1 "2 "2 -)" %xternal (/34
physical layer ST7570 20/26 doc id 17526 rev 2 9 physical layer the ST7570 embeds a iec-61334-5-1 phy layer, which is based on the s-fsk (spread fsk) modulation technique. 9.1 s-fsk principles the s-fsk modulation technique is aimed at strengthening the classical fsk by adding higher robustness against narrow-band interferers typical of a spread-spectrum approach. non-return-to-zero (nrz) coding is used to map the binary data ?0? or ?1? to sinusoidal carriers at frequencies f 0 and f 1 ( figure 11 ). figure 11. s-fsk waveform (time domain) the absolute frequency deviation |f 0 - f 1 | is at least 10 khz, in order to reduce the probability that a narrow-band interferer could corrupt both carriers at the same time. f 0 and f 1 can be set at any value in cenelec bands a, b, d. figure 12. s-fsk waveform (frequency domain) !-v i i _i i _!n+]
ST7570 physical layer doc id 17526 rev 2 21/26 9.2 bit timing the data communication is synchronized to the mains zero-crossing through an internal pll. the bit time is dynamically adapted in order to have always 24 or 48 bits in each mains cycle, according to the desired configuration ( figure 13 ). the resulting bit-rate is thus dependent on the instantaneous mains frequency. with a nominal frequency of 50 hz, the resulting bit-rate is 1200 bps in the case of 24 bit/mains cycle, while 2400 bps in the case of 48 bit/mains cycle. figure 13. bit timing !-v :ero crossing :ero crossing -ainscycle bitmainscycle bpsat (z bpsat (z bitmainscycle bpsat (z bpsat (z -ainswaveform (zor (z
physical layer ST7570 22/26 doc id 17526 rev 2 9.3 frame structure at physical level the frame at physical level is compliant with the iec61334-5-1 and is composed of 45 bytes (360 bits) as follows: 2 byte preamble (pre) (aaaah); 2 byte start subframe delimiter (ssd) (54c7h); 38 byte physical service data unit (p_sdu); 3 byte for pause or alarm; the bytes are sent from the most significant byte (msb) to the least significant byte (lsb). bits within the byte are packed with the same order (msb to lsb). figure 14. physical frame format 9.4 frame timing and time-slot synchronization the iec61334-5-1 protocol specifies a master-slave network with time-division medium access: in order to properly communicate, all the nodes belonging to a network must share the same ?slot synchronization?. the time division is fixed through the use of time-slots, corresponding to a physical frame length of 45 bytes (i.e. 360 bits) with a total duration equal to: 15 mains cycles, at the 1200 bps operating speed (at 50 hz); 7.5 mains cycles, at the 2400 bps operating speed (at 50 hz). the slot synchronization is first achieved by the master (i.e. ST7570 modem in 'client' mode) setting the time-slot starting at the mains zero-crossing instant. the frames transmitted by the master will enable the slot synchronization of all other slave nodes (i.e. ST7570 working in 'server' mode): the reception of the sequence composed by pre and ssd will allow all the 'server' nodes aligning their time-slots to the client's time-slot. !-v 3uhdpeoh 35( 6wduw6xeiudph 'holplwhu 66' 3bvgx 3dxvh$odup e\whv e\whv e\whv elw 3+<)udph
ST7570 package mechanical data doc id 17526 rev 2 23/26 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. the ST7570 is hosted in a 48 pin thermally enhanced very thin fine pitch quad flat package no lead (vfqfpn) with exposed pad, which allows the device dissipating the heat that is generated by the operation of the two linear regulators and the power amplifier. a mechanical drawing of the vfqfpn48 package is included in figure 15 . table 9. vfqfpn48 (7 x 7 x 1.0 mm) package mechanical data dim. (mm) min. typ. max. a 0.80 0.90 1.00 a1 0.02 0.05 a2 0.65 1.00 a3 0.25 b 0.18 0.23 0.30 d 6.85 7.00 7.15 d2 4.95 5.10 5.25 e 6.85 7.00 7.15 e2 4.95 5.10 5.25 e 0.45 0.50 0.55 l 0.30 0.40 0.50 ddd 0.08
package mechanical data ST7570 24/26 doc id 17526 rev 2 figure 15. vfqfpn48 (7 x 7 x 1.0 mm) package outline
ST7570 revision history doc id 17526 rev 2 25/26 11 revision history table 10. document revision history date revision changes 27-may-2010 1 initial release. 24-sep-2012 2 added specifications about erdf linky requirements in features introduction in the coverpage and functional specifications in chapter 8 . updated pinout in table 2 , electrical values in ta bl e 5 .
ST7570 26/26 doc id 17526 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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